1. Field of the Invention
This invention relates to afield effect transistor and its manufacturing method, and more particularly, to a hetero-junctioned semiconductor field effect transistor provided with a conductive channel consisting of very fine electron accumulated-layer stripes and its manufacturing method.
2. Description of the Prior Art
The recent development in the technology to grow crystals on a compound semiconductor including the molecular beam epitaxial (MBE) growth method has made it possible to atomically control the layer thickness. This technology can also be used to form a hetero junction of semiconductor layers different in nature and selectively dope the semiconductor layer smaller in electron affinity with impurities so that a highly mobile electron accumulated layer may be generated near the aforementioned hetero junction interface within the layer larger in electron affinity. This field effect transistor (FET) using the electron accumulated layer as a current channel is called "hetero-junctioned FET" or "selectively doped FET" and some excellent in high-frequency response have already been put into practical use.
In anticipation of a further increase in the mobility of electrons to be implemented by the conversion of conventional two-dimensional distribution of electrons to one-dimensional distribution, an attempt has been to made to manufacture a FET provided with such a one-dimensionally distributed electron channel. In 1989, Onda, et al. reported on such an FET in IEDM Technical Digest pp. 125-128. A reported FET example is shown in FIG. 1-FIG. 3 and other one in FIG. 4-FIG. 6.
In FIG. 1-FIG. 3, the FET is provided with a high-purity GaAs layer 2, an undoped AlGaAs layer 4a as a spacer, a N-type AlGaAs layer 4 which supplies electrons to an electron accumulated layer 3 generated within the high-purity GaAs layer 2, and a N-type GaAs layer 5 formed in that order by an MBE method on a primary surface of a semi-insulated GaAs substrate. On the surface of the N-type GaAs layer 5, a source electrode 6 and a drain electrode 7 are formed with a channel area therebetween. Within the channel area on the N-type GaAs layer 5, a gate electrode 8 is formed almost in the center between the source electrode 6 and the drain electrode 7.
In the aforementioned channel area, the undoped AlGaAs layer 4a, the N-type AlGaAs layer 4, and the the N-type GaAs layer 5 are partially etched to form grooves 15 called mesas, as shown in FIG. 2. At the bottoms of the grooves 15, the high-purity GaAs layer 2 is exposed. Thus, on the aforementioned channel area, the undoped AlGaAs layer 4a, the N-type AlGaAs layer 4, and the N-type GaAs layer 5 are divided into multiple fine strips 10 with a width of 0.1-1 .mu.m a These strips 10 are formed so as to bridge the source electrode 6 and the drain electrode 7.
Within the high-purity GaAs layer 2, an electron accumulated layer 3 is generated near the interface with the undoped AlGaAs layer 4a. The electron accumulated layer 3 is located only below each of the strips 10 but not below each of the grooves 15. The electron accumulated layer 3 become a conductive channel of the PET. The voltage applied to the gate electrode 8 modulates the potentials of the N-type GaAs layer 5 and the N-type AlGaAs layer 4 to control the current flowing through the electron accumulated layers.
A conventional FET illustrated in FIG. 4-FIG. 6 has almost the same configuration as the aforesaid FET on FIG. 1-FIG. 3 In these figures of both FETs, an element of one FET has the same number as its counterpart of the other. The FET of FIG. 4-FIG. 6 differs from the one of FIG. 1-FIG. 3 in that the former's groove 15a has a roughly rectangular cross section while the latter's groove 15 has a roughly trapezoidal cross section. The other configurations are the same.
It is reported that the aforementioned conventional FETs are both much more excellent in transconductance (gm) at a low temperature and cut-off frequency (fT) than those having no finely divided channel area. It is, therefore, considered that one-dimensional distribution of the electron accumulated layers implemented by finely dividing the conductive channel is quite effective in improving the high-frequency response of the hetero-junctioned FET.
A problem in these conventional FETs is that it is difficult to form a further minute conductive channel with a width of 0.1 .mu.m or less which generates quantum interference effects as a conductive channel is finely divided through the formation of grooves 15 by etching.
Another fine processing-related problem includes a reduced yield rate due to easy formation of a defective gate electrode 8 or 8a on the stepped channel area with grooves 15.
Moreover, it is difficult to form between the source electrode 6 and the drain electrode 7 the grooves of a so-called "recess structure" generally used to reduce series resistance and it is also impossible to increase the impurity concentration in the N-type GaAs 5 layer to prevent the current from leaking from the gate electrode 8 or 8a as the electrodes 8 or 8a form a Schottky junction with the layer 5 This results in a further problem of a failure to obtain expected performance because of larger resistance between the source electrode 6 and the gate electrode 7 than a hetero-junctioned FET whose conductive channel is not finely divided.
Hence, an object of this invention is to provide an FET having a conductive channel with a width of 0.1 .mu.m or less which generates electron quantum interference effects and a method to manufacture such an FET at a favorable yield rate.
Another object of this invention is to provide an FET whose series resistance between the source and the gate electrodes is smaller than a conventional FET whose conductive channel is not finely divided and a method to manufacture such a FET at a favorable yield rate.